FIG. 6 shows a cross-sectional view of a wafer for explaining a prior art method of diffusing Si. In FIG. 6, reference numeral 1 designates an Al.sub.x Ga.sub.1-x As layer (0.ltoreq.x&lt;1) a III - V group compound semiconductor layer. A Si film 2 is disposed on a surface of the Al.sub.x Ga.sub.1-x As layer 1, for example, such vacuum evaporation, CVD (Chemical Vapor Deposition), or sputtering. A protection layer 3 comprising, for example, SiO.sub.2 or Si.sub.3 N.sub.4, disposed on layer 1 and film 2 for protecting the surfaces of the Al.sub.x Ga.sub.1-x As layer 1 and the Si film 2. Si may be diffused into layer 1 without providing this protection layer 3. Reference numeral 5 designates a region into which Si has been diffused.
The Al.sub.x Ga.sub.1-x As layer 1 having Si film 2 thereon is heated up to a temperature of about 800.degree. to 950.degree. C. in an ambient having arsenic (As) partial pressure of about 0.3 atmosphere. Then, Si diffuses into the Al.sub.x Ga.sub.1-x As layer 1 at the elevated temperature.
In this prior art diffusion method, diffusion time, diffusion temperature, arsenic pressure, Si film thickness, protection layer thickness, and the material of the protection layer can be selected as desired, as parameters which determine the diffusion speed and diffusion depth. For example, when the diffusion temperature is low, the arsenic pressure is low, the Si film is thick, and the protection layer is thick, the diffusion speed is low. The reason why the diffusion speed is low when the protection layer is thick is described in "1986 International Conference on Solid State Devices and Materials, pp 41 to 44". Since the annealing is conducted in an As ambient, As diffuses through the protection layer and reaches the interface between the protection layer and GaAs layer, thereby creating (that is, Ga vacancies in the GaAs layer. Si diffuses in association with these vacancies, so that the vacancies promote Si diffusion. When the protection layer is thick, As slowly reaches the interface, thereby lowering the diffusion speed.
Furthermore, it is reported in "Applied Physics Letters", Volume 44(8), Apr. 15, 1984, pp 750 to 752 and the "Journal of the Electrochemical Society", Volume 129, No. 4, 1982, pp 837 to 840 that the diffusion speed is lower when using a Si.sub.3 N.sub.4 protection layer than when using a SiO.sub.2 protection layer. When a SiO.sub.2 protection layer is used, Ga in the GaAs layer is likely to diffuse into SiO.sub.2 at the SiO.sub.2 protection and GaAs layer interface during annealing. Thus, Ga vacancies will occur in the GaAs layer and Si will diffuse in association with these vacancies, thereby promoting the diffusion. On the other hand, when a Si.sub.3 N.sub.4 protection layer is used, Ga is not likely to diffuse into Si.sub.3 N.sub.4. In addition, since annealing is conducted in an As ambient, As will diffuse through the protection layer and reach the SiO.sub.2 protection and GaAs layer interface, thereby creating an As rich region in GaAs layer. Since Si diffuses in association with the resulting Ga vacancies, diffusion is promoted. Since an Si.sub.3 N.sub.4 film is denser than SiO.sub.2, As more slowly reaches the interface, thereby reducing the diffusion speed.
When the Si diffusion process is employed in making a device, the diffusion depth needs to be precisely controlled. In the prior art diffusion method, however, since the diffusion depth depends on many parameters as described above, it is difficult to control the diffusion depth with a high degree of reproducibility and precision by suppressing variations of these parameters.